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MX29LV640D T/B
64M-BIT [8M x 8/4M x 16] SINGLE VOLTAGE 3V ONLY FLASH MEMORY
FEATURES
GENERAL FEATURES * 8,388,608 x 8 / 4,194,304 x 16 switchable * Sector Structure - 8KB(4KW) x 8 and 64KB(32KW) x 127 * Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable * Sector Groups Protection / Chip Unprotect - Provides sector group protect function to prevent program or erase operation in the protected sector group - Provides chip unprotect function to allow code changing - Provides temporary sector group unprotect function for code changing in previously protected sector groups * Single Power Supply Operation - 2.7 to 3.6 volt for read, erase, and program operations * Latch-up protected to 100mA from -1V to 1.5 x Vcc * Low Vcc write inhibit : Vcc <= Vlko * Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash PERFORMANCE * High Performance - Fast access time: 90ns - Fast program time: 11us/word (typical) - Fast erase time: 0.7s/sector, 45s/chip (typical) * Low Power Consumption - Low active read current: 9mA (typical) at 5MHz - Low standby current: 5uA (typical) * 100,000 erase/program cycle (typical) * 10 years data retention SOFTWARE FEATURES * Erase Suspend/ Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased * Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion * Support Common Flash Interface (CFI) HARDWARE FEATURES * Ready/Busy# (RY/BY#) Output - Provides a hardware method of detecting program and erase operation completion * Hardware Reset (RESET#) Input - Provides a hardware method to reset the internal state machine to read mode * WP#/ACC input pin - Provides accelerated program capability
P/N:PM1208
REV. 1.6, AUG. 16, 2008
1
MX29LV640D T/B
PACKAGE * 44-Pin SOP * 48-Pin TSOP * 48-Ball LFBGA * All Pb-free devices are RoHS Compliant
PIN CONFIGURATION
44 SOP
A21 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# Q0 Q8 Q1 Q9 Q2 Q10 Q3 Q11 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A20 A19 A8 A9 A10 A11 A12 A13 A14 A15 A16 WE# GND Q15 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC
48 TSOP
A15 A14 A13 A12 A11 A10 A9 A8 A19 A20 WE# RESET# A21 WP#/ACC RY/BY# A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE# GND Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE# GND CE# A0
MX29LV640D T/B
MX29LV640D T/B
48-Ball LFBGA 6mm x 8mm (Ball Pich=0.8mm), Top View, Balls Facing Down
A B C D E F G H
6
A13
A12
A14
A15
A16
BYTE#
Q15/ A-1
GND
5
A9
A8
A10
A11
Q7
Q14
Q13
Q6
4
WE#
RESET# WP#/ ACC A17
A21
A19
Q5
Q12
VCC
Q4 6.0 mm
3
RY/ BY#
A18
A20
Q2
Q10
Q11
Q3
2
A7
A6
A5
Q0
Q8
Q9
Q1
1
A3
A4
A2
A1
A0
CE#
OE#
GND
8.0 mm
P/N:PM1208
REV. 1.6, AUG. 16, 2008
2
MX29LV640D T/B
PIN DESCRIPTION
SYMBOL A0~A21 Q0~Q14 Q15/A-1 CE# WE# OE# RESET# BYTE# PIN NAME Address Input Data Inputs/Outputs Q15(Word Mode)/LSB addr(Byte Mode) Chip Enable Input Write Enable Input Output Enable Input Hardware Reset Pin, Active Low Word/Byte Selection Input Acceleration Input RY/BY# VCC GND Read/Busy Output +3.0V single power supply Device Ground
CE# OE# WE# RESET# RY/BY# WP#/ACC BYTE#
LOGIC SYMBOL
22 A0-A21 Q0-Q15 (A-1) 16 or 8
WP#/ACC Hardware Write Protect/Programming
P/N:PM1208
REV. 1.6, AUG. 16, 2008
3
MX29LV640D T/B
BLOCK DIAGRAM
CE# OE# WE# RESET# BYTE# WP#/ACC
WRITE CONTROL INPUT LOGIC HIGH VOLTAGE MACHINE (WSM) PROGRAM/ERASE STATE
X-DECODER
STATE FLASH ARRAY ARRAY REGISTER
ADDRESS LATCH A0-AM AND BUFFER
SENSE AMPLIFIER
Y-DECODER
Y-PASS GATE
SOURCE HV COMMAND DATA DECODER
PGM DATA HV COMMAND DATA LATCH
PROGRAM DATA LATCH
Q0-Q15/A-1
I/O BUFFER
AM: MSB address
P/N:PM1208
REV. 1.6, AUG. 16, 2008
4
MX29LV640D T/B
Table 1. BLOCK STRUCTURE
MX29LV640DT SECTOR GROUP ARCHITECTURE Sector Group 1 1 1 1 2 2 2 2 3 3 3 3 4 4 4 4 5 5 5 5 6 6 6 6 7 7 7 7 8 8 8 8 9 9 9 9 10 10 10 10
P/N:PM1208
Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32
Sector
Sector Address A21-A12 0000000xxx 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011100xxx 0011101xxx 0011110xxx 0011111xxx 0100000xxx 0100001xxx 0100010xxx 0100011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx
Address Range Byte Mode (x8) Word Mode (x16) 000000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 000000h-07FFFh 008000h-0FFFFh 010000h-17FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh
REV. 1.6, AUG. 16, 2008
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38 SA39
5
MX29LV640D T/B
Sector Group 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 16 17 17 17 17 18 18 18 18 19 19 19 19 20 20 20 20 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector Sector Address A21-A12 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx Address Range Byte Mode (x8) Word Mode (x16) 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-147FFFh 168000h-14FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-247FFFh 268000h-24FFFFh 270000h-277FFFh 278000h-27FFFFh
SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78 SA79
P/N:PM1208
REV. 1.6, AUG. 16, 2008
6
MX29LV640D T/B
Sector Group 21 21 21 21 22 22 22 22 23 23 23 23 24 24 24 24 25 25 25 25 26 26 26 26 27 27 27 27 28 28 28 28 29 29 29 29 30 30 30 30 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector Sector Address A21-A12 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx Address Range Byte Mode (x8) Word Mode (x16) 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-347FFFh 368000h-34FFFFh 370000h-377FFFh 378000h-37FFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh
SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118 SA119
P/N:PM1208
REV. 1.6, AUG. 16, 2008
7
MX29LV640D T/B
Sector Group 31 31 31 31 32 32 32 33 34 35 36 37 38 39 40 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 Sector Sector Address A21-A12 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111000 1111111001 1111111010 1111111011 1111111100 1111111101 1111111110 1111111111 Address Range Byte Mode (x8) Word Mode (x16) 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7F1FFFh 7F2000h-7F3FFFh 7F4000h-7F5FFFh 7F6000h-7F7FFFh 7F8000h-7F9FFFh 7FA000h-7FBFFFh 7FC000h-7FDFFFh 7FE000h-7FFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh 3F9000h-3F9FFFh 3FA000h-3FAFFFh 3FB000h-3FBFFFh 3FC000h-3FCFFFh 3FD000h-3FDFFFh 3FE000h-3FEFFFh 3FF000h-3FFFFFh
SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
Top Boot Security Sector Addresses
Sector Size Byte Mode Word Mode (bytes) (words) 256 128 Sector Address A21~A12 1111111111 Address Range Byte Mode (x8) Word Mode (x16) 7FFF00h-7FFFFFh 3FFF80h-3FFFFFh
P/N:PM1208
REV. 1.6, AUG. 16, 2008
8
MX29LV640D T/B
MX29LV640DB SECTOR GROUP ARCHITECTURE Sector Group 1 2 3 4 5 6 7 8 9 9 9 10 10 10 10 11 11 11 11 12 12 12 12 13 13 13 13 14 14 14 14 15 15 15 15 16 16 16 16 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 8 4 8 4 8 4 8 4 8 4 8 4 8 4 8 4 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector Sector Address A21-A12 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001xxx 0000010xxx 0000011xxx 0000100xxx 0000101xxx 0000110xxx 0000111xxx 0001000xxx 0001001xxx 0001010xxx 0001011xxx 0001100xxx 0001101xxx 0001110xxx 0001111xxx 0010000xxx 0010001xxx 0010010xxx 0010011xxx 0010100xxx 0010101xxx 0010110xxx 0010111xxx 0011000xxx 0011001xxx 0011010xxx 0011011xxx 0011100xxx 0011101xxx 0011110xxx 0011111xxx Address Range Byte Mode (x8) Word Mode (x16) 000000h-001FFFh 002000h-003FFFh 004000h-005FFFh 006000h-007FFFh 008000h-009FFFh 00A000h-00BFFFh 00C000h-00DFFFh 00E000h-00FFFFh 010000h-01FFFFh 020000h-02FFFFh 030000h-03FFFFh 040000h-04FFFFh 050000h-05FFFFh 060000h-06FFFFh 070000h-07FFFFh 080000h-08FFFFh 090000h-09FFFFh 0A0000h-0AFFFFh 0B0000h-0BFFFFh 0C0000h-0CFFFFh 0D0000h-0DFFFFh 0E0000h-0EFFFFh 0F0000h-0FFFFFh 100000h-10FFFFh 110000h-11FFFFh 120000h-12FFFFh 130000h-13FFFFh 140000h-14FFFFh 150000h-15FFFFh 160000h-16FFFFh 170000h-17FFFFh 180000h-18FFFFh 190000h-19FFFFh 1A0000h-1AFFFFh 1B0000h-1BFFFFh 1C0000h-1CFFFFh 1D0000h-1DFFFFh 1E0000h-1EFFFFh 1F0000h-1FFFFFh 000000h-000FFFh 001000h-001FFFh 002000h-002FFFh 003000h-003FFFh 004000h-004FFFh 005000h-005FFFh 006000h-006FFFh 007000h-007FFFh 008000h-00FFFFh 010000h-017FFFh 018000h-01FFFFh 020000h-027FFFh 028000h-02FFFFh 030000h-037FFFh 038000h-03FFFFh 040000h-047FFFh 048000h-04FFFFh 050000h-057FFFh 058000h-05FFFFh 060000h-067FFFh 068000h-06FFFFh 070000h-077FFFh 078000h-07FFFFh 080000h-087FFFh 088000h-08FFFFh 090000h-097FFFh 098000h-09FFFFh 0A0000h-0A7FFFh 0A8000h-0AFFFFh 0B0000h-0B7FFFh 0B8000h-0BFFFFh 0C0000h-0C7FFFh 0C8000h-0CFFFFh 0D0000h-0D7FFFh 0D8000h-0DFFFFh 0E0000h-0E7FFFh 0E8000h-0EFFFFh 0F0000h-0F7FFFh 0F8000h-0FFFFFh
SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 SA20 SA21 SA22 SA23 SA24 SA25 SA26 SA27 SA28 SA29 SA30 SA31 SA32 SA33 SA34 SA35 SA36 SA37 SA38
P/N:PM1208
REV. 1.6, AUG. 16, 2008
9
MX29LV640D T/B
Sector Group 17 17 17 17 18 18 18 18 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23 23 23 23 24 24 24 24 25 25 25 25 26 26 26 26 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector Sector Address A21-A12 0100000xxx 0100001xxx 0100010xxx 0100011xxx 0100100xxx 0100101xxx 0100110xxx 0100111xxx 0101000xxx 0101001xxx 0101010xxx 0101011xxx 0101100xxx 0101101xxx 0101110xxx 0101111xxx 0110000xxx 0110001xxx 0110010xxx 0110011xxx 0110100xxx 0110101xxx 0110110xxx 0110111xxx 0111000xxx 0111001xxx 0111010xxx 0111011xxx 0111100xxx 0111101xxx 0111110xxx 0111111xxx 1000000xxx 1000001xxx 1000010xxx 1000011xxx 1000100xxx 1000101xxx 1000110xxx 1000111xxx Address Range Byte Mode (x8) Word Mode (x16) 200000h-20FFFFh 210000h-21FFFFh 220000h-22FFFFh 230000h-23FFFFh 240000h-24FFFFh 250000h-25FFFFh 260000h-26FFFFh 270000h-27FFFFh 280000h-28FFFFh 290000h-29FFFFh 2A0000h-2AFFFFh 2B0000h-2BFFFFh 2C0000h-2CFFFFh 2D0000h-2DFFFFh 2E0000h-2EFFFFh 2F0000h-2FFFFFh 300000h-30FFFFh 310000h-31FFFFh 320000h-32FFFFh 330000h-33FFFFh 340000h-34FFFFh 350000h-35FFFFh 360000h-36FFFFh 370000h-37FFFFh 380000h-38FFFFh 390000h-39FFFFh 3A0000h-3AFFFFh 3B0000h-3BFFFFh 3C0000h-3CFFFFh 3D0000h-3DFFFFh 3E0000h-3EFFFFh 3F0000h-3FFFFFh 400000h-40FFFFh 410000h-41FFFFh 420000h-42FFFFh 430000h-43FFFFh 440000h-44FFFFh 450000h-45FFFFh 460000h-46FFFFh 470000h-47FFFFh 100000h-107FFFh 108000h-10FFFFh 110000h-117FFFh 118000h-11FFFFh 120000h-127FFFh 128000h-12FFFFh 130000h-137FFFh 138000h-13FFFFh 140000h-147FFFh 148000h-14FFFFh 150000h-157FFFh 158000h-15FFFFh 160000h-167FFFh 168000h-16FFFFh 170000h-177FFFh 178000h-17FFFFh 180000h-187FFFh 188000h-18FFFFh 190000h-197FFFh 198000h-19FFFFh 1A0000h-1A7FFFh 1A8000h-1AFFFFh 1B0000h-1B7FFFh 1B8000h-1BFFFFh 1C0000h-1C7FFFh 1C8000h-1CFFFFh 1D0000h-1D7FFFh 1D8000h-1DFFFFh 1E0000h-1E7FFFh 1E8000h-1EFFFFh 1F0000h-1F7FFFh 1F8000h-1FFFFFh 200000h-207FFFh 208000h-20FFFFh 210000h-217FFFh 218000h-21FFFFh 220000h-227FFFh 228000h-22FFFFh 230000h-237FFFh 238000h-23FFFFh
SA39 SA40 SA41 SA42 SA43 SA44 SA45 SA46 SA47 SA48 SA49 SA50 SA51 SA52 SA53 SA54 SA55 SA56 SA57 SA58 SA59 SA60 SA61 SA62 SA63 SA64 SA65 SA66 SA67 SA68 SA69 SA70 SA71 SA72 SA73 SA74 SA75 SA76 SA77 SA78
P/N:PM1208
REV. 1.6, AUG. 16, 2008
10
MX29LV640D T/B
Sector Group 27 27 27 27 28 28 28 28 29 29 29 29 30 30 30 30 31 31 31 31 32 32 32 32 33 33 33 33 34 34 34 34 35 35 35 35 36 36 36 36 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector Sector Address A21-A12 1001000xxx 1001001xxx 1001010xxx 1001011xxx 1001100xxx 1001101xxx 1001110xxx 1001111xxx 1010000xxx 1010001xxx 1010010xxx 1010011xxx 1010100xxx 1010101xxx 1010110xxx 1010111xxx 1011000xxx 1011001xxx 1011010xxx 1011011xxx 1011100xxx 1011101xxx 1011110xxx 1011111xxx 1100000xxx 1100001xxx 1100010xxx 1100011xxx 1100100xxx 1100101xxx 1100110xxx 1100111xxx 1101000xxx 1101001xxx 1101010xxx 1101011xxx 1101100xxx 1101101xxx 1101110xxx 1101111xxx Address Range Byte Mode (x8) Word Mode (x16) 480000h-48FFFFh 490000h-49FFFFh 4A0000h-4AFFFFh 4B0000h-4BFFFFh 4C0000h-4CFFFFh 4D0000h-4DFFFFh 4E0000h-4EFFFFh 4F0000h-4FFFFFh 500000h-50FFFFh 510000h-51FFFFh 520000h-52FFFFh 530000h-53FFFFh 540000h-54FFFFh 550000h-55FFFFh 560000h-56FFFFh 570000h-57FFFFh 580000h-58FFFFh 590000h-59FFFFh 5A0000h-5AFFFFh 5B0000h-5BFFFFh 5C0000h-5CFFFFh 5D0000h-5DFFFFh 5E0000h-5EFFFFh 5F0000h-5FFFFFh 600000h-60FFFFh 610000h-61FFFFh 620000h-62FFFFh 630000h-63FFFFh 640000h-64FFFFh 650000h-65FFFFh 660000h-66FFFFh 670000h-67FFFFh 680000h-68FFFFh 690000h-69FFFFh 6A0000h-6AFFFFh 6B0000h-6BFFFFh 6C0000h-6CFFFFh 6D0000h-6DFFFFh 6E0000h-6EFFFFh 6F0000h-6FFFFFh 240000h-247FFFh 248000h-24FFFFh 250000h-257FFFh 258000h-25FFFFh 260000h-267FFFh 268000h-26FFFFh 270000h-277FFFh 278000h-27FFFFh 280000h-287FFFh 288000h-28FFFFh 290000h-297FFFh 298000h-29FFFFh 2A0000h-2A7FFFh 2A8000h-2AFFFFh 2B0000h-2B7FFFh 2B8000h-2BFFFFh 2C0000h-2C7FFFh 2C8000h-2CFFFFh 2D0000h-2D7FFFh 2D8000h-2DFFFFh 2E0000h-2E7FFFh 2E8000h-2EFFFFh 2F0000h-2F7FFFh 2F8000h-2FFFFFh 300000h-307FFFh 308000h-30FFFFh 310000h-317FFFh 318000h-31FFFFh 320000h-327FFFh 328000h-32FFFFh 330000h-337FFFh 338000h-33FFFFh 340000h-347FFFh 348000h-34FFFFh 350000h-357FFFh 358000h-35FFFFh 360000h-367FFFh 368000h-36FFFFh 370000h-377FFFh 378000h-37FFFFh
SA79 SA80 SA81 SA82 SA83 SA84 SA85 SA86 SA87 SA88 SA89 SA90 SA91 SA92 SA93 SA94 SA95 SA96 SA97 SA98 SA99 SA100 SA101 SA102 SA103 SA104 SA105 SA106 SA107 SA108 SA109 SA110 SA111 SA112 SA113 SA114 SA115 SA116 SA117 SA118
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Sector Group 37 37 37 37 38 38 38 38 39 39 39 39 40 40 40 40 Sector Size Byte Mode Word Mode (Kbytes) (Kwords) 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 64 32 Sector Sector Address A21-A12 1110000xxx 1110001xxx 1110010xxx 1110011xxx 1110100xxx 1110101xxx 1110110xxx 1110111xxx 1111000xxx 1111001xxx 1111010xxx 1111011xxx 1111100xxx 1111101xxx 1111110xxx 1111111xxx Address Range Byte Mode (x8) Word Mode (x16) 700000h-70FFFFh 710000h-71FFFFh 720000h-72FFFFh 730000h-73FFFFh 740000h-74FFFFh 750000h-75FFFFh 760000h-76FFFFh 770000h-77FFFFh 780000h-78FFFFh 790000h-79FFFFh 7A0000h-7AFFFFh 7B0000h-7BFFFFh 7C0000h-7CFFFFh 7D0000h-7DFFFFh 7E0000h-7EFFFFh 7F0000h-7FFFFFh 380000h-387FFFh 388000h-38FFFFh 390000h-397FFFh 398000h-39FFFFh 3A0000h-3A7FFFh 3A8000h-3AFFFFh 3B0000h-3B7FFFh 3B8000h-3BFFFFh 3C0000h-3C7FFFh 3C8000h-3CFFFFh 3D0000h-3D7FFFh 3D8000h-3DFFFFh 3E0000h-3E7FFFh 3E8000h-3EFFFFh 3F0000h-3F7FFFh 3F8000h-3FFFFFh
SA119 SA120 SA121 SA122 SA123 SA124 SA125 SA126 SA127 SA128 SA129 SA130 SA131 SA132 SA133 SA134
Bottom Boot Security Sector Addresses
Sector Size Byte Mode Word Mode (bytes) (words) 256 128 Sector Address A21~A12 0000000000 Address Range Byte Mode (x8) Word Mode (x16) 000000h-0000FFh 000000h-00007Fh
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Table 2. BUS OPERATION--1 Mode Select RESET# CE# WE# OE# Address Data (I/O) Q0~Q7 Device Reset Standby Mode Output Disable Read Mode Write(Note1) Accelerate Program Temporary Sector-Group Unprotect Sector-Group Protect (Note2) Chip Unprotect (Note2) Vhv L L H Vhv L L H Sector Address, DIN, DOUT A6=L, A1=H, A0=L Sector Address, DIN, DOUT A6=H, A1=H, A0=L X X Note3 X X L/H Vhv X X X AIN DIN H H H L L L H L L L H H AIN AIN AIN DOUT DIN DIN Q8-Q14= HighZ, Q15= A-1 HighZ DIN Note3 DOUT DIN DIN L/H Note3 Vhv L Vcc 0.3V H X Vcc 0.3V L H H X HighZ HighZ HighZ L/H X X X X X X HighZ HighZ Byte# Vil Vih Data (I/O) Q8~Q15 HighZ HighZ HighZ HighZ L/H H WP#/ ACC
Notes: 1. All sectors will be unprotected if WP#/ACC=Vhv. 2. The two outmost boot sectors are protected if WP#/ACC=Vil. 3. When WP#/ACC = Vih, the protection conditions of the two outmost boot sectors depend on previous protection conditions."Sector/Sector Block Protection and Unprotection" describes the protect and unprotect method. 4. Q0~Q15 are input (DIN) or output (DOUT) pins according to the requests of command sequence, sector protection, or data polling algorithm. 5. In Word Mode (Byte#=Vih), the addresses are AM to A0. In Byte Mode (Byte#=Vil), the addresses are AM to A-1 (Q15). 6. AM: MSB of address.
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BUS OPERATION--2 Item Control Input CE# WE# OE# AM to A11 to A9 A8 to A7 Vhv x L A6 A5 to A2 x H L 01h or 00h (Note1) Read Silicon ID Manufacturer Code Read Silicon ID MX29LV640DT Read Silicon ID MX29LV640DB Read Indicator Bit (Q7) For Security Sector Notes: 1. Sector unprotected code:00h. Sector protected code:01h. 2. Factory locked code: WP# protects bottom two address sector: 88h. WP# protects top two address sector: 98h Factory unlocked code: WP# protects bottom two address sector: 08h. WP# protects top two address sector: 18h 3. AM: MSB of address. L H L x x Vhv x L x H H (Note2) L H L x x Vhv x L x L H CBh L H L x x Vhv x L x L H C9h 22h(Word) XXh(Byte) 22h(Word) XXh(Byte) x L H L x x Vhv x L x L L C2h x x A1 A0 Q0~Q7 Q8~Q15
A12 A10 Sector Lock Status Verification L H L SA x
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WRITE COMMANDS/COMMAND SEQUENCES To write a command to the device, system must drive WE# and CE# to Vil, and OE# to Vih. In a command cycle, all address are latched at the later falling edge of CE# and WE#, and all data are latched at the earlier rising edge of CE# and WE#. Figure 1 illustrates the AC timing waveform of a write command, and Table 3 defines all the valid command sets of the device. System is not allowed to write invalid commands not defined in this datasheet. Writing an invalid command will bring the device to an undefined state.
REQUIREMENTS FOR READING ARRAY DATA Read array action is to read the data stored in the array. While the memory device is in powered up or has been reset, it will automatically enter the status of read array. If the microprocessor wants to read the data stored in the array, it has to drive CE# (device enable control pin) and OE# (Output control pin) as Vil, and input the address of the data to be read into address pin at the same time. After a period of read cycle (Tce or Taa), the data being read out will be displayed on output pin for microprocessor to access. If CE# or OE# is Vih, the output will be in tri-state, and there will be no data displayed on output pin at all. After the memory device completes embedded operation (automatic Erase or Program), it will automatically return to the status of read array, and the device can read the data in any address in the array. In the process of erasing, if the device receives the Erase suspend command, erase operation will be stopped temporarily after a period of time no more than Tready and the device will return to the status of read array. At this time, the device can read the data stored in any address except the sector being erased in the array. In the status of erase suspend, if user wants to read the data in the sectors being erased, the device will output status data onto the output. Similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased. The device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. In program or erase operation, the programming or erasing failure causes Q5 to go high. 2. The device is in auto select mode or CFI mode. In the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data.
ACCELERATED PROGRAM OPERATION The accelerated program can improve programming performance compared with word/byte program. By applying Vhv on WP#/ACC pin, the device will enter accelerated program and draw current no more than Icp1 from WP#/ACC pin. Removing the Vhv from WP#/ACC pin will put the device back to normal operation (not accelerated).
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RESET# OPERATION Driving RESET# pin low for a period more than Trp will reset the device back to read mode. If the device is in program or erase operation, the reset operation will take at most a period of Tready for the device to return to read array mode. Before the device returns to read array mode, the RY/BY# pin remains low (busy status). When RESET# pin is held at GND0.3V, the device consumes standby current(Isb).However, device draws larger current if RESET# pin is held at Vil but not within GND0.3V. It is recommended that the system to tie its reset signal to RESET# pin of flash memory, so that the flash memory will be reset during system reset and allows system to read boot code from flash memory.
SECTOR GROUP PROTECT OPERATION When a sector group is protected, program or erase operation will be disabled on these sectors. MX29LV640D T/B provides two methods for sector group protection. Once the sector group is protected, the sector group remains protected until next chip unprotect, or is temporarily unprotected by asserting RESET# pin at Vhv. Refer to temporary sector group unprotect operation for further details. The first method is by applying Vhv on RESET# pin. Refer to Figure 13 for timing diagram and Figure 14 for the algorithm for this method. The other method is asserting Vhv on A9 and OE# pins, with A6 and CE# at Vil. The protection operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
CHIP UNPROTECT OPERATION MX29LV640D T/B provides two methods for chip unprotect. The chip unprotect operation unprotects all sectors within the device. It is recommended to protect all sectors before activating chip unprotect mode. All sectors groups are unprotected when shipped from the factory. The first method is by applying Vhv on RESET# pin. Refer to Figure 13 for timing diagram and Figure 14 for algorithm of the operation. The other method is asserting Vhv on A9 and OE# pins, with A6 at Vih and CE# at Vil. The unprotect operation begins at the falling edge of WE# and terminates at the rising edge. Contact Macronix for details.
TEMPORARY SECTOR GROUP UNPROTECT OPERATION System can apply RESET# pin at Vhv to place the device in temporary unprotect mode. In this mode, previously protected sectors can be programmed or erased just as it is unprotected. The devices returns to normal operation once Vhv is removed from RESET# pin and previously protected sectors are again protected.
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WRITE PROTECT (WP#) Another function of the WP#/ACC pin is to provide write protection function on the two outermost 8 Kbyte boot sectors. When ViL is asserted on WP#/ACC pin, the two boot sectors are protected regardless of the previous state of protection implemented by aforementioned Sector Group Protect/Chip Unprotect. For MX29LV640DT, the two outermost sectors are the two boot sectors of the highest addresses. For MX29LV640DB, the two outermost sectors are the two boot sectors of the lowest addresses. Note that the WP#/ACC should be either Vhv, Vih, or Vil, and must not be floated or unconnected; otherwise the device may not function properly.
AUTOMATIC SELECT OPERATION When the device is in Read array mode, erase-suspended read array mode or CFI mode, user can issue read silicon ID command to enter read silicon ID mode. After entering read silicon ID mode, user can query several silicon IDs continuously and does not need to issue read silicon ID mode again. When A0 is Low, device will output Macronix Manufacture ID C2H. When A0 is high, device will output Device ID. In read silicon ID mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. Another way to enter read silicon ID is to apply high voltage on A9 pin with CE#, OE#, A6 and A1 at Vil. While the high voltage of A9 pin is discharged, device will automatically leave read silicon ID mode and go back to read array mode or erase-suspended read array mode. When A0 is Low, device will output Macronix Manufacture ID C2. When A0 is high, device will output Device ID.
VERIFY SECTOR GROUP PROTECT STATUS OPERATION MX29LV640D T/B provides hardware sector protection against Program and Erase operation for protected sectors. The sector protect status can be read through Sector Protect Verify command. This method requires Vhv on A9 pin, Vih on WE# and A1 pins, Vil on CE#, OE#, A6 and A0 pins, and sector address on A12 to A21 pins. If the read out data is 01H, the designated sector is protected. Oppositely, if the read out data is 00H, the designated sector is not protected.
SECURITY SECTOR FLASH MEMORY REGION The Security Sector region is an extra memory space of 128 words in length. The security sectors can be locked upon shipping from factory, or it can be locked by customer after shipping. Customer can issue Security Sector Factory Protect Verify and/or Security Sector Protect Verify to query the lock status of the device. In factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". In customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0".
Factory Locked: Security Sector Programmed and Protected at the Factory In a factory locked device, the security silicon region is permanently locked after shipping from factory. The device will have a 16-byte (8-word) ESN in the security region. In bottom boot device : 000000h - 000007h (for MX29LV640DB).In Top boot device : 3FFF70h - 3FFF77h (for MX29LV640DT).
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Customer Lockable: Security Sector NOT Programmed or Protected at the Factory When the security feature is not required, the security region can act as an extra memory space. Security silicon sector can also be protected by two methods. Note that once the security silicon sector is protected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. The first method is to write a three-cycle command of Enter Security Region, and then follow the sector group protect algorithm as illustrated in Figure 14, except that RESET# pin may at either Vih or Vhv. The other method is to write a three-cycle command of Enter Security Region, and then follow the alternate method of sector protect with A9, OE# at Vhv. After the security silicon is locked and verified, system must write Exit Security Sector Region, go through a power cycle, or issue a hardware reset to return the device to read normal array mode.
DATA PROTECTION To avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. Besides, only after successful completion of the specified command sets will the device begin its erase or program operation. Other features to protect the data from accidental alternation are described as followed.
LOW VCC WRITE INHIBIT The device refuses to accept any write command when Vcc is less than Vlko. This prevents data from spuriously altered. The device automatically resets itself when Vcc is lower than Vlko and write cycles are ignored until Vcc is greater than Vlko. System must provide proper signals on control pins after Vcc is larger than Vlko to avoid unintentional program or erase operation
WRITE PULSE "GLITCH" PROTECTION CE#, WE#, OE# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle.
LOGICAL INHIBIT A valid write cycle requires both CE# and WE# at Vil with OE# at Vih. Write cycle is ignored when either CE# at Vih, WE# a Vih, or OE# at Vil.
POWER-UP SEQUENCE Upon power up, MX29LV640D T/B is placed in read array mode. Furthermore, program or erase operation will begin only after successful completion of specified command sequences.
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POWER-UP WRITE INHIBIT When WE#, CE# is held at Vil and OE# is held at Vih during power up, the device ignores the first command on the rising edge of WE#.
POWER SUPPLY DECOUPLING A 0.1uF capacitor should be connected between the Vcc and GND to reduce the noise effect.
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TABLE 3. MX29LV640D T/B COMMAND DEFINITIONS
Automatic Select Read Mode Addr Data 2nd Bus Cyc 3rd Bus Cyc Addr Data Addr Data 4th Bus Cyc Addr Data 5th Bus Cyc 6th Bus Cyc Addr Data Addr Data Addr Data Reset Mode XXX F0 Security Sector Factory Protect Verify Word 555 AA 2AA 55 555 90 X03 98/18(T) 88/08(B) Byte AAA AA 555 55 AAA 90 X06 98/18(T) 88/08(B) Sector Protect Verify Word 555 AA 2AA 55 555 90 Byte AAA AA 555 55 AAA 90 Enter Security Sector Region Enable Word 555 AA 2AA 55 555 88 Byte AAA AA 555 55 AAA 88
Command 1st Bus Cyc
Silicon ID Word 555 AA 2AA 55 555 90 X00 C2H Byte AAA AA 555 55 AAA 90 X00 C2H
Device ID Word 555 AA 2AA 55 555 90 X01 ID Byte AAA AA 555 55 AAA 90 X02 ID
(Sector) (Sector) X02 X04 00/01 00/01
Command 1st Bus Cyc 2nd Bus Cyc 3rd Bus Cyc 4th Bus Cyc 5th Bus Cyc 6th Bus Cyc Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data
Exit Security Sector 555 AA 2AA 55 555 90 XXX 00 AAA AA 555 55 AAA 90
Program 555 AA 2AA 55 555 A0 AAA AA 555 55 AAA A0
Chip Erase 555 AA 2AA 55 555 80 555 AA 2AA 55 555 10 AAA AA 555 55 AAA 80 AAA AA 555 55 10
Sector Erase Word 555 AA 2AA 55 555 80 555 AA 2AA 55 30 Byte AAA AA 555 55 AAA 80 AAA AA 555 55 Sector 30
CFI Read 55 98 AA 98
Erase Suspend XXX B0
Erase Resume Word/Byte XXX 30
Word Byte Word Byte Word Byte
Word Byte Word/Byte
XXX Addr Addr 00 Data Data
AAA Sector
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RESET In the following situations, executing reset command will reset device back to read array mode: * Among erase command sequence (before the full command set is completed) * Sector erase time-out period * Erase fail (while Q5 is high) * Among program command sequence (before the full command set is completed, erase-suspended program included) * Program fail (while Q5 is high, and erase-suspended program fail is included) * Read silicon ID mode * Sector protect verify * CFI mode While device is at the status of program fail or erase fail (Q5 is high), user must issue reset command to reset device back to read array mode. While the device is in read silicon ID mode, sector protect verify or CFI mode, user must issue reset command to reset device back to read array mode. When the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ignore reset command.
AUTOMATIC SELECT COMMAND SEQUENCE Automatic Select mode is used to access the manufacturer ID, device ID and to verify whether or not secured silicon is locked and whether or not a sector is protected. The automatic select mode has four command cycles. The first two are unlock cycles, and followed by a specific command. The fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. The reset command is necessary to exit the Automatic Select mode and back to read array. The following table shows the identification code with corresponding address. Address Manufacturer ID Device ID Secured Silicon Word Byte Word Byte Word Byte Sector Protect Verify Word Byte X00 X00 X01 X02 X03 X06 (Sector address) X 02 (Sector address) X 04 Data (Hex) C2 C2 22C9/22CB C9/CB 98/18 (T) 88/08 (B) 98/18 (T) 88/08 (B) 00/01 00/01 Unprotected/protected Unprotected/protected Factory locked/unlocked Top/Bottom Boot Sector Top/Bottom Boot Sector Factory locked/unlocked Representation
There is an alternative method to that shown in Table 2, which is intended for EPROM programmers and requires Vhv on address bit A9.
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AUTOMATIC PROGRAMMING The MX29LV640D T/B can provide the user program function by the form of Byte-Mode or Word-Mode. As long as the users enter the right cycle defined in the Table.3 (including 2 unlock cycles and A0H), any data user inputs will automatically be programmed into the array. Once the program function is executed, the internal write state controller will automatically execute the algorithms and timings necessary for program and verification, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verification. Meanwhile, the internal control will prohibit the programming to cells that pass verification while the other cells fail in verification in order to avoid over-programming. With the internal write state controller, the device requires the user to write the program command and data only. Programming will only change the bit status from "1" to "0". That is to say, it is impossible to convert the bit status from "0" to "1" by programming. Meanwhile, the internal write verification only detects the errors of the "1" that is not successfully programmed to "0". Any command written to the device during programming will be ignored except hardware reset, which will terminate the program operation after a period of time no more than Tready. When the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. The typical chip program time at room temperature of the MX29LV640D T/B is less than 45 seconds. When the embedded program operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress*1 Finished Exceed time limit Q7 Q7# Q7 Q7# Q6 togging Stop toggling Toggling Q5 0 0 1 RY/BY#*2 0 1 0
*1: The status "in progress" means both program mode and erase-suspended program mode. *2: RY/BY# is an open drain output pin and should be weakly connected to VDD through a pull-up resistor. *3: When an attempt is made to program a protected sector, Q7 will output its complement data or Q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the protected sector.
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CHIP ERASE Chip Erase is to erase all the data with "1" and "0" as all "1". It needs 6 cycles to write the action in, and the first two cycles are "unlock" cycles, the third one is a configuration cycle, the fourth and fifth are also "unlock" cycles, and the sixth cycle is the chip erase operation. During chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. After Chip Erase, the chip will return to the state of Read Array. When the embedded chip erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status In progress Finished Exceed time limit Q7 0 1 0 Q6 Togging Stop toggling Toggling Q5 0 0 1 Q2 Toggling 1 Toggling RY/BY# 0 1 0
SECTOR ERASE Sector Erase is to erase all the data in a sector with "1" and "0" as all "1". It requires six command cycles to issue. The first two cycles are "unlock cycles", the third one is a configuration cycle, the fourth and fifth are also "unlock cycles" and the sixth cycle is the sector erase command. After the sector erase command sequence is issued, there is a timeout period of 50us counted internally. During the time-out period, additional sector address and sector erase command can be written multiply. Once user enters another sector erase command, the time-out period of 50us is recounted. If user enters any command other than sector erase or erase suspend during time-out period, the erase command would be aborted and the device is reset to read array condition. The number of sectors could be from one sector to all sectors. After time-out period passing by, additional erase command is not accepted and erase embedded operation begins. During sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. When the embedded erase operation is on going, user can confirm if the embedded operation is finished or not by the following methods: Status Time-out period In progress Finished Exceed time limit Q7 0 0 1 0 Q6 Togging Togging Stop toggling Toggling Q5 0 0 0 1 Q3 0 1 1 1 Q2 Toggling Toggling 1 Toggling RY/BY#*2 0 0 1 0
Note : 1. The status Q3 is the time-out period indicator. When Q3=0, the device is in time-out period and is acceptible to another sector address to be erased. When Q3=1, the device is in erase operation and only erase suspend is valid.
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2. RY/BY# is open drain output pin and should be weakly connected to VDD through a pull-up resistor. 3. When an attempt is made to erase a protected sector, Q7 will output its complement data or Q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. 4. Q2 is a localized indicator showing a specified sector is undergoing erase operation or not. Q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). When a sector has been completely erased, Q2 stops toggling at the sector even when the device is still in erase operation for remaining selected sectors. At that circumstance, Q2 will still toggle when device is read at any other sector that remains to be erased.
SECTOR ERASE SUSPEND During sector erasure, sector erase suspend is the only valid command. If user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erasesuspended read array mode. If user issue erase suspend command during the sector erase is being operated, device will suspend the ongoing erase operation, and after the Tready1 (<=20us) suspend finishes and the device will enter erase-suspended read array mode. User can judge if the device has finished erase suspend through Q6, Q7, and RY/ BY#. After device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of Taa; while reading the sector in erase-suspend mode, device will output its status. Whenever a suspend command is issued, user must issue a resume command and check Q6 toggle bit status, before issue another erase command. The system can use the status register bits shown in the following table to determine the current state of the device: Status Erase suspend read in erase suspended sector Erase suspend read in non-erase suspended sector Erase suspend program in non-erase suspended sector Q7 1 Data Q7# Q6 No toggle Data Toggle Q5 0 Data 0 Q3 N/A Data N/A Q2 toggle Data N/A RY/BY# 1 1 0
When the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon ID, sector protect verify, program, CFI query and erase resume.
SECTOR ERASE RESUME Sector erase resume command is valid only when the device is in erase suspend state. After erase resume, user can issue another erase suspend command, but there should be a 4ms interval between erase resume and the next erase suspend. If user issue infinite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase.
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MX29LV640D T/B
QUERY COMMAND AND COMMON FLASH INTERFACE (CFI) MODE MX29LV640D T/B features CFI mode. Host system can retrieve the operating characteristics, structure and vendorspecified information such as identifying information, memory size, byte/word configuration, operating voltages and timing information of this device by CFI mode. The device enters the CFI Query mode when the system writes the CFI Query command, 98H, to address 55H/AAH (depending on Word/Byte mode) any time the device is ready to read array data. The system can read CFI information at the addresses given in Table 4. A reset command is required to exit CFI mode and go back to ready array mode or erase suspend mode. The system can write the CFI Query command only when the device is in read mode, erase suspend, standby mode or automatic select mode.
Table 4-1. CFI mode: Identification Data Values (All values in these tables are in hexadecimal) Description Query-unique ASCII string "QRY" Address (h) (Word Mode) 10 11 12 13 14 15 16 17 18 19 1A Address (h) (Byte Mode) 20 22 24 26 28 2A 2C 2E 30 32 34 Data (h) 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000
Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code Address for alternate algorithm extended query table
Table 4-2. CFI Mode: System Interface Data Values Description Vcc supply minimum program/erase voltage Vcc supply maximum program/erase voltage VPP supply minimum program/erase voltage VPP supply maximum program/erase voltage Typical timeout per single word/byte write, 2n us Typical timeout for maximum-size buffer write, 2n us Typical timeout per individual block erase, 2n ms Typical timeout for full chip erase, 2n ms Maximum timeout for word/byte write, 2n times typical Maximum timeout for buffer write, 2n times typical Maximum timeout per individual block erase, 2n times typical Maximum timeout for chip erase, 2n times typical
P/N:PM1208
Address (h) (Word Mode) 1B 1C 1D 1E 1F 20 21 22 23 24 25 26
Address (h) (Byte Mode) 36 38 3A 3C 3E 40 42 44 46 48 4A 4C
Data (h) 0027 0036 0000 0000 0004 0000 000A 0000 0005 0000 0004 0000
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Table 4-3. CFI Mode: Device Geometry Data Values Description Device size = 2 in number of bytes Flash device interface description (02=asynchronous x8/x16) Maximum number of bytes in buffer write = 2 (not support) Number of erase regions within device Index for Erase Bank Area 1 [2E,2D] = # of same-size sectors in region 1-1 [30, 2F] = sector size in multiples of 256-bytes Index for Erase Bank Area 2
n n
Address (h) (Word Mode) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34
Address (h) (Byte Mode) 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78
Data (h) 0017 0002 0000 0000 0000 0002 0007 0000 0020 0000 007E 0000 0000 0001 0000 0000 0000 0000 0000 0000 0000 0000
Index for Erase Bank Area 3
35 36 37 38
Index for Erase Bank Area 4
39 3A 3B 3C
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Table 4-4. CFI Mode: Primary Vendor-Specific Extended Query Data Values Description Query - Primary extended table, unique ASCII string, PRI Address (h) (Word Mode) 40 41 42 Major version number, ASCII Minor version number, ASCII Unlock recognizes address (0= recognize, 1= don't recognize) Erase suspend (2= to both read and program) Sector protect (N= # of sectors/group) Temporary sector unprotect (1=supported) Sector protect/Chip unprotect scheme Simultaneous R/W operation (0=not supported) Burst mode (0=not supported) Page mode (0=not supported) [D3:D0] for 100mV Maximum ACC (acceleration) supply (0= not supported), [D7:D4] for volt, 4E [D3:D0] for 100mV Top/Bottom boot block indicator 02h=bottom boot device 03h=top boot device 4F 9E 0002/ 0003 9C 00C5 43 44 45 46 47 48 49 4A 4B 4C Address (h) (Byte Mode) 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A 0050 0052 0049 0031 0031 0000 0002 0004 0001 0004 0000 0000 0000 00B5 Data (h)
Minimum ACC (acceleration) supply (0= not supported), [D7:D4] for volt, 4D
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ABSOLUTE MAXIMUM STRESS RATINGS
Surrounding Temperature with Bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +125oC Storage Temperature . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65oC to +150oC Voltage Range Vcc . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +4.0 V RESET#, A9, ACC and OE# . .. . . . . . .. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.5 V to +11.5 V The other pins. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.5 V to Vcc +0.5 V Output Short Circuit Current (less than one second) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .200 mA Note: 1. Minimum voltage may undershoot to -2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to Vcc+2V during transition and for less than 20ns during transitions.
OPERATING TEMPERATURE AND VOLTAGE
Commercial (C) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 C to +70 C Industrial (I) Grade Surrounding Temperature (TA ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40 C to +85 C VCC Supply Voltages VCC range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +2.7 V to 3.6 V
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DC CHARACTERISTICS
Symbol Iilk Iilk9 Iolk Icr1 Icr2 Icw Description Input Leak A9 Leak Output Leak Read Current(5MHz) Read Current(1MHz) Write Current 9mA 2mA 26mA Min Typ Max 1.0uA 35uA 1.0uA 16mA 4mA 30mA CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih CE#=Vil, OE#=Vih, WE#=Vil Isb Isbr Standby Current Reset Current 5uA 5uA 15uA 15uA Vcc=Vcc max, other pin disable Vcc=Vccmax, Reset# enable, other pin disable Isbs Icp1 Icp2 Vil Vih Vhv Sleep Mode Current Accelerated Pgm Current, WP#/Acc pin(Word/Byte) Accelerated Pgm Current, Vcc pin,(Word/Byte) Input Low Voltage Input High Voltage Very High Voltage for hardware Protect/Unprotect/Auto Select/ Temporary Unprotect/ Accelerated Program Vol Voh1 Voh2 Vlko Output Low Voltage Ouput High Voltage Ouput High Voltage Low Vcc Lock-out Voltage 0.85xVcc Vcc-0.4V 2.3V 2.5V 0.45V Iol=4.0mA Ioh1=-2mA Ioh2=-100uA -0.5V 0.7xVcc 9.5V 0.8V Vcc+0.3V 10.5V 15mA 30mA 5uA 5mA 15uA 10mA CE#=Vil, OE#=Vih, CE#=Vil, OE#=Vih, A9=10.5V Remark
P/N:PM1208
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SWITCHING TEST CIRCUITS
Vcc
0.1uF
TESTED DEVICE
R2 +3.3V
R1
CL
DIODES=IN3064 OR EQUIVALENT
R1=6.2K ohm R2=2.7K ohm
Test Condition Output Load : 1 TTL gate Output Load Capacitance,CL : 30pF Rise/Fall Times : 5ns In/Out reference levels :1.5V
SWITCHING TEST WAVEFORMS
3.0V
1.5V
1.5V
Test Points 0.0V INPUT
OUTPUT
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AC CHARACTERISTICS
Symbol Taa Tce Toe Tdf Toh Trc Twc Tcwc Tas Tah Tds Tdh Tvcs Tcs Tch Toes Toeh Toeh Tws Twh Tcep Tceph Twp Twph Tbusy Tghwl Tghel Twhwh1 Twhwh1 Twhwh1 Twhwh2 Tbal Output enable hold time WE# setup time WE# hold time CE# pulse width CE# pulse width high WE# pulse width WE# pulse width high Program/Erase active time by RY/BY# Read recover time before write Read recover time before write Program operation Program operation Acc Program operation(Word/Byte) Sector Erase Operation Sector Add hold time Byte Word 0 0 9 11 7 0.7 50 Description Valid data output after address Valid data output after CE# low Valid data output after OE# low Data output floating after OE# high (*Note 1) Output hold time from the earliest rising edge of address, CE#, OE# Read period time Write period time Command write period time Address setup time Address hold time Data setup time Data hold time Vcc setup time Chip enable Setup time Chip enable hold time Output enable setup time Read Toggle & Data# Polling 0 0 45 30 35 30 90 ns ns ns ns ns ns ns ns ns us us us sec us 90 90 90 0 45 45 0 200 0 0 0 0 10 ns ns ns ns ns ns ns us ns ns ns ns ns 0 Min Typ Max 90 90 30 16 Unit ns ns ns ns ns
* Note 1: Sampled only, not 100% tested.
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MX29LV640D T/B
Figure 1. COMMAND WRITE OPERATION
Tcwc
CE#
Vih Vil Tcs Tch
WE#
Vih Vil Toes Twp Twph
OE#
Vih Vil
Addresses
Vih
VA
Vil Tas Tds Vih Tah Tdh
Data
Vil
DIN
VA: Valid Address
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READ/RESET OPERATION
Figure 2. READ TIMING WAVEFORMS
Tce Vih
CE#
Vil
Vih
WE#
Vil Vih
Toeh
Toe
Tdf
OE#
Vil Taa Trc Vih Toh
Addresses
Vil
ADD Valid
Outputs
Voh Vol
HIGH Z
DATA Valid
HIGH Z
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AC CHARACTERISTICS Item Trp1 Trp2 Trh Trb1 Trb2 Tready1 Tready2 Description RESET# Pulse Width (During Automatic Algorithms) RESET# Pulse Width (NOT During Automatic Algorithms) RESET# High Time Before Read RY/BY# Recovery Time (to CE#, OE# go low) RY/BY# Recovery Time (to WE# go low) RESET# PIN Low (During Automatic Algorithms) to Read or Write RESET# PIN Low (NOT During Automatic Algorithms) to Read or Write MAX 500 ns Setup MIN MIN MIN MIN MIN MAX Speed 10 500 50 0 50 20 Unit us ns ns ns ns us
Figure 3. RESET# TIMING WAVEFORM
Trb1
CE#, OE#
Trb2
WE#
Tready1
RY/BY# RESET#
Trp1
Reset Timing during Automatic Algorithms
CE#, OE#
Trh
RY/BY#
RESET#
Trp2 Tready2
Reset Timing NOT during Automatic Algorithms
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MX29LV640D T/B
ERASE/PROGRAM OPERATION
Figure 4. AUTOMATIC CHIP ERASE TIMING WAVEFORM
CE#
Tch Twp
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Erase Command Cycle
Twc Tas Tah
Read Status
Address
2AAh
SA
VA
VA
Tds
Tdh
In Progress Complete
55h Data
10h
Tbusy
Trb
RY/BY#
SA: 555h for chip erase
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MX29LV640D T/B
Figure 5. AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 10H Address 555H
Data# Polling Algorithm or Toggle Bit Algorithm
NO
Data=FFh ?
YES
Auto Chip Erase Completed
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Figure 6. AUTOMATIC SECTOR ERASE TIMING WAVEFORM
Read Status
CE#
Tch Twp Twhwh2
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Erase Command Cycle
Twc Tas
Tbal
Address
2AAh
Tds Tdh
Sector Address 0
Tah
Sector Address 1
Sector Address n
VA
VA
In Progress Complete
55h Data
30h
30h
30h
Tbusy Trb
RY/BY#
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Figure 7. AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 80H Address 555H
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data 30H Sector Address
Last Sector to Erase YES Data# Polling Algorithm or Toggle Bit Algorithm
NO
Data=FFh
NO
YES
Auto Sector Erase Completed
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MX29LV640D T/B
Figure 8. ERASE SUSPEND/RESUME FLOWCHART
START
Write Data B0H
NO Toggle Bit checking Q6 not toggled YES Read Array or Program
ERASE SUSPEND
Reading or Programming End YES Write Data 30H
NO
ERASE RESUME Continue Erase
Another Erase Suspend ? YES
NO
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Figure 9. AUTOMATIC PROGRAM TIMING WAVEFORMS
CE#
Tch Twp Twhwh1
WE#
Tcs
Twph
Tghwl
OE#
Last 2 Program Command Cycle
Tas Tah
Last 2 Read Status Cycle
Address
555h
PA
VA
VA
Tds
Tdh
A0h Data
PD
Status
DOUT
Tbusy
Trb
RY/BY#
Figure 10. Accelerated Program Timing Diagram
(9.5V ~ 10.5V) Vhv
WP#/ACC
Vil or Vih Vil or Vih
250ns
250ns
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Figure 11. CE# CONTROLLED WRITE TIMING WAVEFORM
WE#
Tcep
Twhwh1 or Twhwh2
CE#
Tceph
Tghwl
OE#
Tas
Tah
Address
555h
PA
VA
VA
Tds
Tdh
A0h Data
PD
Status
DOUT
Tbusy
RY/BY#
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Figure 12. AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART
START
Write Data AAH Address 555H
Write Data 55H Address 2AAH
Write Data A0H Address 555H
Write Program Data/Address
Data# Polling Algorithm or Toggle Bit Algorithm next address
Read Again Data: Program Data? YES
No
No
Last Word to be Programed YES
Auto Program Completed
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SECTOR GROUP PROTECT/CHIP UNPROTECT
Figure 13. SECTOR GROUP PROTECT/CHIP UNPROTECT WAVEFORM (RESET# Control)
1us
150uS: Sector Protect 15mS: Chip Unprotect
CE#
WE#
OE# Verification Data 60h 60h 40h Status
SA, A6 A1, A0
VA
VA
VA
Vhv Vih
RESET# VA: valid address
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Figure 14-1. IN-SYSTEM SECTOR GROUP PROTECT WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect Mode
No First CMD=60h?
Yes Write Sector Address with [A6,A1,A0]:[0,1,0] data: 60h
Wait 150us
Write Sector Address with [A6,A1,A0]:[0,1,0] data: 40h Retry Count +1 Read at Sector Address with [A6,A1,A0]:[0,1,0] No No Retry Count=25?
Reset PLSCNT=1
Data=01h?
Yes Device fail
Yes Yes
Protect another sector? No Temporary Unprotect Mode
RESET#=Vih
Write RESET CMD
Sector Protect Done
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Figure 14-2. CHIP UNPROTECT ALGORITHMS WITH RESET#=Vhv
START
Retry count=0
RESET#=Vhv
Wait 1us
Temporary Unprotect
No First CMD=60h?
Yes
All sectors protected? Yes
No
Protect All Sectors
Write [A6,A1,A0]:[1,1,0] data: 60h
Wait 15ms
Retry Count +1
Write [A6,A1,A0]:[1,1,0] data: 40h
Read [A6,A1,A0]:[1,1,0] No No Retry Count=1000? Data=00h?
Yes Device fail
Yes Temporary Unprotect
Write reset CMD
Chip Unprotect Done
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Table 5. TEMPORARY SECTOR GROUP UNPROTECT Parameter Trpvhh Tvhhwl Alt Tvidr Trsp Description RESET# Rise Time to Vhv and Vhv Fall Time to RESET# RESET# Vhv to WE# Low Condition MIN MIN Speed 500 4 Unit ns us
Figure 15. TEMPORARY SECTOR GROUP UNPROTECT WAVEFORMS
Program or Erase Command Sequence
CE#
WE#
Tvhhwl
RY/BY#
Vhv
10V
RESET#
0 or Vih Vil or Vih
Trpvhh
Trpvhh
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MX29LV640D T/B
Figure 16. TEMPORARY SECTOR GROUP UNPROTECT FLOWCHART
Start
Apply Reset# pin Vhv Volt
Enter Program or Erase Mode
Mode Operation Completed
(1) Remove Vhv Volt from Reset# (2) RESET# = Vih
Completed Temporary Sector Unprotected Mode
Notes: 1. Temporary unprotect all protected sectors Vhv=9.5~10.5V. 2. After leaving temporary unprotect mode, the previously protected sectors are again protected.
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MX29LV640D T/B
Figure 17. SILICON ID READ TIMING WAVEFORM
Vih
CE#
Vil Tce Vih
WE#
Vil Vih Toe Tdf Toh Toh
OE#
Vil
Vhv
A9
Vih Vil
Vih
A0
Vil Taa Taa
A1
Vih Vil
Vih
ADD
Vil
DATA Q0-Q7 (Byte Mode)
Vih
DATA OUT
Vil
DATA OUT C9h (TOP boot) CBh (Bottom boot)
C2h
DATA Q0-Q15/A-1 (Word Mode)
Vih
DATA OUT
Vil
DATA OUT 22C9h (TOP boot) 22CBh (Bottom boot)
00C2h
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MX29LV640D T/B
WRITE OPERATION STATUS
Figure 18. DATA# POLLING TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh Tdf Trc
Address
Taa Toh
VA
VA
Q7 Q0-Q6
Tbusy
Status Data
Complement
True
Valid Data
High Z
Status Data
Status Data
True
Valid Data
High Z
RY/BY#
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MX29LV640D T/B
Figure 19. DATA# POLLING ALGORITHM
Start
Read Q7~Q0 at valid address (Note 1)
No Q7 = Data# ?
Yes No
Q5 = 1 ?
Yes Read Q7~Q0 at valid address
Q7 = Data# ? (Note 2) Yes FAIL
No
Pass
Notes: 1. For programming, valid address meas program address. For erasing, valid address meas erase sectors address. 2. Q7 should be rechecked even Q5="1" because Q7 may change simultaneously with Q5.
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MX29LV640D T/B
Figure 20. TOGGLE BIT TIMING WAVEFORMS (DURING AUTOMATIC ALGORITHMS)
Tce
CE#
Tch
WE#
Toe
OE#
Toeh Tdf
Trc
Address
VA
Taa Toh
VA
VA
VA
Q6/Q2
Tbusy
Valid Status (first read)
Valid Status (second read)
Valid Data (stops toggling)
Valid Data
RY/BY#
VA : Valid Address
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MX29LV640D T/B
Figure 21. TOGGLE BIT ALGORITHM
Start
Read Q7-Q0 Twice
(Note 1)
Q6 Toggle ?
NO
YES
NO Q5 = 1?
YES
Read Q7~Q0 Twice
NO Q6 Toggle ?
YES
PGM/ERS fail Write Reset CMD
PGM/ERS Complete
Notes: 1. Read toggle bit twice to determine whether or not it is toggling. 2. Recheck toggle bit because it may stop toggling as Q5 changes to "1".
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AC CHARACTERISTICS WORD/BYTE CONFIGURATION (BYTE#) Parameter Telfl/Telfh Tflqz Tfhqv Description CE# to BYTE# from L/H BYTE# from L to Output Hiz BYTE# from H to Output Active MAX MAX MIN Speed 90 5 30 90 ns ns ns Unit
Figure 22. BYTE# TIMING WAVEFORM FOR READ OPERATIONS (BYTE# switching from byte mode to word mode)
CE#
OE#
Telfh
BYTE#
Q0~Q14
DOUT (Q0-Q7)
DOUT (Q0-Q14)
Q15/A-1
VA Tfhqv
DOUT (Q15)
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RECOMMENDED OPERATING CONDITIONS
At Device Power-Up AC timing illustrated in Figure A is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
Vcc(min)
Vcc
GND
Tvr
Tvcs Tf Tce Tr
Vih
CE#
Vil
Vih
WE#
Vil
Tf
Vih
Toe
Tr
OE#
Vil
Tr or Tf
Vih
Taa
Tr or Tf
ADDRESS
Vil
Valid Address
Voh
DATA
High Z
Vol
Valid Ouput
Vih
WP#/ACC
Vil
Figure A. AC Timing at Device Power-Up
Symbol Tvr Tr Tf Tvcs
Parameter Vcc Rise Time Input Signal Rise Time Input Signal Fall Time Vcc Setup Time
Min. 20
Max. 500000 20 20
Unit us/V us/V us/V us
200
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ERASE AND PROGRAMMING PERFORMANCE
LIMITS PARAMETER Chip Erase Time Sector Erase Time Erase/Program Cycles Chip Programming Time Byte Mode Word Mode Accelerated Byte/Word Program Time Word Program Time Byte Programming Time MIN. TYP. 45 0.7 100,000 50 45 7 11 9 160 140 210 360 300 MAX. 65 2 UNITS sec sec Cycles sec sec us us us
Notes: 1. Typical program and erase times assume the following conditions: 25 C, 3.0V VCC. Programming specifications assume checkboard data pattern. 2. Maximum values are measured at VCC = 3.0 V, worst case temperature. Maximum values are valid up to and including 100,000 program/erase cycles. 3. Word/Byte programming specification is based upon a single word/byte programming operation not utilizing the write buffer. 4. Erase/Program cycles comply with JEDEC JESD-47E & A117A standard.
LATCH-UP CHARACTERISTICS
MIN. Input Voltage voltage difference with GND on WP#/ACC, A9, OE, Reset# pins Input Voltage voltage difference with GND on all normal pins input Input Current Pulse All pins included. Test conditions: Vcc = 3.0V, one pin per testing -1.0V -1.0V -100mA MAX. 11.5V Vcc x 1.5V +100mA
TSOP PIN CAPACITANCE
Parameter Symbol CIN2 COUT CIN Parameter Description Control Pin Capacitance Output Capacitance Input Capacitance Test Set VIN=0 VOUT=0 VIN=0 TYP 7.5 8.5 6 MAX 9 12 7.5 UNIT pF pF pF
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ORDERING INFORMATION
PART NO. MX29LV640DTMC-90G MX29LV640DBMC-90G MX29LV640DTTC-90G MX29LV640DBTC-90G MX29LV640DTXEC-90G MX29LV640DBXEC-90G MX29LV640DTXEI-90G MX29LV640DBXEI-90G MX29LV640DTTI-90G MX29LV640DBTI-90G ACCESS TIME (ns) 90 90 90 90 90 90 90 90 90 90 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.4mm 0.8mm/0.4mm Ball Pitch/ Ball size 44 Pin SOP 44 Pin SOP 48 Pin TSOP(Normal Type) 48 Pin TSOP(Normal Type) 48 Ball LFBGA 48 Ball LFBGA 48 Ball LFBGA 48 Ball LFBGA 48 Pin TSOP(Normal Type) 48 Pin TSOP(Normal Type) Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free Pb-free PACKAGE Remark
* 44-pin SOP is only for Pachinko Socket
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PART NAME DESCRIPTION
MX 29 LV 640 D T T C
90 G
OPTION: G: Lead-free package SPEED: 90: 90ns TEMPERATURE RANGE: C: Commercial (0C to 70C) I: Industrial (-40C to 85C) PACKAGE: M:SOP T: TSOP X: FBGA (CSP) XE - 0.4mm Ball
BOOT BLOCK TYPE: T: Top Boot B: Bottom Boot
REVISION: D DENSITY & MODE: 640: 64M x8/x16 Boot Block
TYPE: LV: 3V DEVICE: 29:Flash
P/N:PM1208
REV. 1.6, AUG. 16, 2008
57
MX29LV640D T/B
PACKAGE INFORMATION
P/N:PM1208
REV. 1.6, AUG. 16, 2008
58
MX29LV640D T/B
P/N:PM1208
REV. 1.6, AUG. 16, 2008
59
MX29LV640D T/B
P/N:PM1208
REV. 1.6, AUG. 16, 2008
60
MX29LV640D T/B
REVISION HISTORY
Revision No. Description Page 1.0 1. Modified Tvcs from 50us(Min.) to 100us(Min.) P31,54 2. Modified latch-up protected to 250mA-->100mA P1 3. Modified latch-up characteristics P1,29,55 4. Modified sector erase resume section ...should be a 400us-->4ms P24 5. Modified "sector erase time" from 0.9s(typ)/15s(max) to P1, 31,55 0.7s(typ)/2s(max) 1.1 1. Erase/ Program test methodology comply with JEDEC standard P1,55 2. Added Byte# mode and removed NC pin of the pin description table P2 3. Added industrial grade information P56,57 1.2 1. Removed 44-sop package information All 2. Modified figure 11. CE# controlled write timing waveform P41 3. Modified Tvcs from 100us to 200us P31,54 4. Added overshoot/undershoot information P28 1.3 1. Added 44-pin SOP package solution P2,56,57 2. Corrected wrong security sector address P8,12 3. Corrected wrong ID code data P21 4. Redefined Trv (Vcc Rise Time) min. spec P54 5. Revised Tdf spec from 30ns(max.) to 16ns(max.) P31 1.4 1. Changed Vhv spec from 10.5V~11.5V to 9.5V~10.5V P29,40,47 2. Added note 1 of AC Characteristics P31 1.5 1. Modified DATA at Silicon ID Dead Timing Waveform P48 1.6 1. Renamed CSP package as LFBGA P2,56 Date MAY/02/2007
SEP/03/2007
OCT/23/2007
JAN/25/2008
APR/08/2008 MAY/29/2008 AUG/15/2008
P/N:PM1208
REV. 1.6, AUG. 16, 2008
61
MX29LV640D T/B
Macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. Macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of Macronix's products in the prohibited applications.
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MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.
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